1. Field of the Invention
The present invention relates to dual workfunction semiconductor devices. More particularly the present invention relates to dual workfunction semiconductor devices having fully silicidized control electrodes. The present invention provides a method for forming dual workfunction semiconductor devices and dual workfunction semiconductor devices thus obtained.
2. Description of the Related Technology
Nowadays CMOS devices are scaling down more and more. In today's CMOS devices the sizes of, for example, gate electrodes become so small that control of charges in a channel of a CMOS device through gate voltage is suppressed by depletion charges in source and drain regions. In order to limit this suppression, capacitance per unit area of the gate electrode may be increased or leakage current may be decreased by using a high-k dielectric material as a gate dielectric. A further improvement may be achieved by using, for example, metal electrodes instead of polysilicon (Poly-Si) electrodes for forming the gate electrode. Through this, depletion effects which typically occur in Poly-Si may be eliminated. Replacing Poly-Si gate electrodes by gate electrodes comprising a metal has two important advantages, i.e. sheet resistance and equivalent electrical thickness of the gate dielectric may be lowered. To replace Poly-Si gate electrodes FUSI (fully silicidized) gate electrodes form a good alternative for metal gate electrodes.
In “Ni and Co based silicides for advanced CMOS applications” (Materials for Advanced Metallization, MAM 2003: Proceedings of the European Workshop on Materials for Advanced Metallization 2003, La Londe Les Maures, France, Mar. 9-12, 2003, vol. 70, no. 2-4, pp. 158-165), J. A. Kittl et al. studied behavior of Co, Co—Ni and Ni silicides in sub-40 nm gate length CMOS technologies with sub-100 nm junction depts. It was found that NiSi has good scaling behavior. NiSi maintains low sheet resistances down to the small gate lengths of about 30 nm. It was furthermore found that Ge pre-amorphization implants before silicidation accelerate the silicidation reaction while N pre-implantation before silicidation slows down the silicidation reaction.
In dual workfunction CMOS devices a PMOS and NMOS device are integrated on a same substrate, adjacent each other. In case the CMOS devices comprise FUSI gates, the PMOS and NMOS devices may comprise different silicide phases providing a different workfunction to the gate electrodes of the PMOS and NMOS. With a silicide phase, a predetermined type of a particular metal silicide is meant, i.e. metal rich (silicon poor) or metal poor (silicon rich) silicide. For example, in case nickel silicide is used to form the gate electrodes a first nickel silicide phase, e.g. Ni2Si or Ni31Si12, may be used for forming the gate electrode of the PMOS and a second nickel silicide phase, e.g. NiSi, may be used to form the gate electrode of the NMOS. Because of the scaling down of these devices, in dual workfunction CMOS devices the different silicide phases of the gates of the PMOS and the NMOS may come in close contact at the transition from NMOS to PMOS. The diffusion length of the metal, in the example given Ni, in the silicides can lead to a change in phase of the gate electrodes and hence a change in threshold voltage Vt of the device. In case of thermal steps being performed in the manufacturing process of the CMOS device after formation of the gates (e.g. a baking step at 400° C.), the metal, in the example given Ni, can diffuse between the gate electrodes of the PMOS and NMOS, and thus modify the optimum phase of the PMOS and NMOS devices. This issue is especially severe in SRAM structures where the minimum distance between NMOS and PMOS devices can be as small as 40 nm.